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Creators/Authors contains: "Cho, Sung-Gun"

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  1. ; ; (, 2019 IEEE Custom Integrated Circuits Conference (CICC))
    A 40nm, 2.56mm2 , 2048-neuron globally asynchronous locally synchronous (GALS) spiking neural network (SNN) chip is presented. For scalability, we allow neurons to specialize to excitatory or inhibitory, and apply distance-based pruning to cut communication and memory. An asynchronous router limits the latency to 1.32ns per hop. The reduced traffic and lower latency allow the input channel to be parallelized to achieve 7.85GSOP/s at 0.7V, consuming 5.9pJ/SOP. 
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  2. ; ; (, IEEE Journal of Solid-State Circuits)
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